Udemy VSD Custom Layout
Seeders : 0 Leechers : 7
| Torrent Hash : | A37735C9E739D5556E8620B1528E81BFEA3A5D64 |
| Torrent Added : | at Oct. 23, 2023, 11:42 p.m. in Other |
| Torrent Size : | 591.1 MB |
Note :
Please Update (Trackers Info) Before Start " Udemy VSD Custom Layout" Torrent Downloading to See Updated Seeders And Leechers for Batter Torrent Download Speed.Torrent File Content (3 files)
Udemy VSD Custom Layout
Get Bonus Downloads Here.url -
001 Course content.mp4 -
001 Course content_en.vtt -
001 Create active regions.mp4 -
001 Create active regions_en.vtt -
002 Formation of N-well and P-well.mp4 -
002 Formation of N-well and P-well_en.vtt -
003 Formation of gate terminal.mp4 -
003 Formation of gate terminal_en.vtt -
004 Lightly doped drain (LDD) formation.mp4 -
004 Lightly doped drain (LDD) formation_en.vtt -
005 Source drain formation.mp4 -
005 Source drain formation_en.vtt -
006 Local interconnect formation.mp4 -
006 Local interconnect formation_en.vtt -
007 Higher level metal formation.mp4 -
007 Higher level metal formation_en.vtt -
001 INV.mag.html -
002 min2.tech.html -
003 Corner stitching introduction.mp4 -
003 Corner stitching introduction_en.vtt -
004 Corner stitch to planes to tiles.mp4 -
004 Corner stitch to planes to tiles_en.vtt -
005 Active tile types and tech file content.mp4 -
005 Active tile types and tech file content_en.vtt -
006 Contacts and styles.mp4 -
006 Contacts and styles_en.vtt -
007 Connect section for circuit extraction.mp4 -
007 Connect section for circuit extraction_en.vtt -
001 Introduction to DRC and lambda design rules.mp4 -
001 Introduction to DRC and lambda design rules_en.vtt -
002 Poly extension and poly to diffusion spacing rules.mp4 -
002 Poly extension and poly to diffusion spacing rules_en.vtt -
003 Poly to diffusion spacing and diffusion contact width rules.mp4 -
003 Poly to diffusion spacing and diffusion contact width rules_en.vtt -
004 Metal1 width and poly to metal1 spacing rules.mp4 -
004 Metal1 width and poly to metal1 spacing rules_en.vtt -
005 Contact spacing and minimum active width rules.mp4 -
005 Contact spacing and minimum active width rules_en.vtt -
006 From logic to layout to SPICE.mp4 -
006 From logic to layout to SPICE_en.vtt -
001 Introduction to simple path, euler's path and euler's circuit.mp4 -
001 Introduction to simple path, euler's path and euler's circuit_en.vtt -
002 Introduction to stick diagram.mp4 -
002 Introduction to stick diagram_en.vtt -
003 Derive actual dimension from stick diagram.mp4 -
003 Derive actual dimension from stick diagram_en.vtt -
001 Pre-layout simulation.mp4 -
001 Pre-layout simulation_en.vtt -
002 Layout using 'only' stick diagram.mp4 -
002 Layout using 'only' stick diagram_en.vtt -
003 Euler's path for Fn - Input gate ordering.mp4 -
003 Euler's path for Fn - Input gate ordering_en.vtt -
004 Improved stick diagram for new gate input ordering.mp4 -
004 Improved stick diagram for new gate input ordering_en.vtt -
005 Abstract layout from stick diagram.mp4 -
005 Abstract layout from stick diagram_en.vtt -
006 Derive actual dimension for Fn.mp4 -
006 Derive actual dimension for Fn_en.vtt -
007 Script to create layout.mp4 -
007 Script to create layout_en.vtt -
008 draw_fn.tcl.html -
009 Final layout and inputoutput labelling.mp4 -
009 Final layout and inputoutput labelling_en.vtt -
001 fn_prelayout.cir.html -
002 fn_postlayout.mag.html -
003 Post-layout simulation and conclusion.mp4 -
003 Post-layout simulation and conclusion_en.vtt -
Bonus Resources.txt -
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Get Bonus Downloads Here.url -
181 bytes
001 Course content.mp4 -
7.4 MB
001 Course content_en.vtt -
6.5 KB
001 Create active regions.mp4 -
16.6 MB
001 Create active regions_en.vtt -
13.9 KB
002 Formation of N-well and P-well.mp4 -
10.8 MB
002 Formation of N-well and P-well_en.vtt -
8.7 KB
003 Formation of gate terminal.mp4 -
14.2 MB
003 Formation of gate terminal_en.vtt -
11.8 KB
004 Lightly doped drain (LDD) formation.mp4 -
12.5 MB
004 Lightly doped drain (LDD) formation_en.vtt -
10.5 KB
005 Source drain formation.mp4 -
7.6 MB
005 Source drain formation_en.vtt -
6.3 KB
006 Local interconnect formation.mp4 -
11.4 MB
006 Local interconnect formation_en.vtt -
9.7 KB
007 Higher level metal formation.mp4 -
16.0 MB
007 Higher level metal formation_en.vtt -
12.6 KB
001 INV.mag.html -
1.3 KB
002 min2.tech.html -
7.9 KB
003 Corner stitching introduction.mp4 -
19.9 MB
003 Corner stitching introduction_en.vtt -
14.2 KB
004 Corner stitch to planes to tiles.mp4 -
16.1 MB
004 Corner stitch to planes to tiles_en.vtt -
11.0 KB
005 Active tile types and tech file content.mp4 -
19.4 MB
005 Active tile types and tech file content_en.vtt -
14.0 KB
006 Contacts and styles.mp4 -
15.9 MB
006 Contacts and styles_en.vtt -
11.6 KB
007 Connect section for circuit extraction.mp4 -
18.3 MB
007 Connect section for circuit extraction_en.vtt -
13.5 KB
001 Introduction to DRC and lambda design rules.mp4 -
22.0 MB
001 Introduction to DRC and lambda design rules_en.vtt -
13.4 KB
002 Poly extension and poly to diffusion spacing rules.mp4 -
26.3 MB
002 Poly extension and poly to diffusion spacing rules_en.vtt -
14.4 KB
003 Poly to diffusion spacing and diffusion contact width rules.mp4 -
20.9 MB
003 Poly to diffusion spacing and diffusion contact width rules_en.vtt -
11.7 KB
004 Metal1 width and poly to metal1 spacing rules.mp4 -
15.5 MB
004 Metal1 width and poly to metal1 spacing rules_en.vtt -
8.4 KB
005 Contact spacing and minimum active width rules.mp4 -
25.1 MB
005 Contact spacing and minimum active width rules_en.vtt -
11.3 KB
006 From logic to layout to SPICE.mp4 -
18.7 MB
006 From logic to layout to SPICE_en.vtt -
11.3 KB
001 Introduction to simple path, euler's path and euler's circuit.mp4 -
16.9 MB
001 Introduction to simple path, euler's path and euler's circuit_en.vtt -
14.3 KB
002 Introduction to stick diagram.mp4 -
18.7 MB
002 Introduction to stick diagram_en.vtt -
14.8 KB
003 Derive actual dimension from stick diagram.mp4 -
41.1 MB
003 Derive actual dimension from stick diagram_en.vtt -
14.1 KB
001 Pre-layout simulation.mp4 -
17.5 MB
001 Pre-layout simulation_en.vtt -
13.1 KB
002 Layout using 'only' stick diagram.mp4 -
17.4 MB
002 Layout using 'only' stick diagram_en.vtt -
14.3 KB
003 Euler's path for Fn - Input gate ordering.mp4 -
12.9 MB
003 Euler's path for Fn - Input gate ordering_en.vtt -
10.7 KB
004 Improved stick diagram for new gate input ordering.mp4 -
15.5 MB
004 Improved stick diagram for new gate input ordering_en.vtt -
12.6 KB
005 Abstract layout from stick diagram.mp4 -
21.0 MB
005 Abstract layout from stick diagram_en.vtt -
14.4 KB
006 Derive actual dimension for Fn.mp4 -
24.8 MB
006 Derive actual dimension for Fn_en.vtt -
15.1 KB
007 Script to create layout.mp4 -
23.1 MB
007 Script to create layout_en.vtt -
14.2 KB
008 draw_fn.tcl.html -
2.6 KB
009 Final layout and inputoutput labelling.mp4 -
51.2 MB
009 Final layout and inputoutput labelling_en.vtt -
14.0 KB
001 fn_prelayout.cir.html -
946 bytes
002 fn_postlayout.mag.html -
3.1 KB
003 Post-layout simulation and conclusion.mp4 -
16.2 MB
003 Post-layout simulation and conclusion_en.vtt -
9.5 KB
Bonus Resources.txt -
386 bytes
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